ai-research-survey

scan.json (28422B)

---

 {
   "paper": {
     "title": "MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs",
     "authors": [
       "Manar Abdelatty",
       "Jingxiao Ma",
       "Sherief Reda"
     ],
     "year": 2025,
     "venue": "30th Asia and South Pacific Design Automation Conference (ASPDAC '25)",
     "arxiv_id": "2411.03471",
     "doi": "10.1145/3658617.3697625"
   },
   "scan_version": 3,
   "active_modules": ["experimental_rigor", "data_leakage"],
   "methodology_tags": ["benchmark-eval"],
   "key_findings": "MetRex introduces a large-scale benchmark of 25,868 Verilog designs annotated with post-synthesis area, delay, and static power metrics. Supervised fine-tuning with Chain of Thought templates improves LLM estimation accuracy by 25-37% across metrics compared to few-shot prompting. Fine-tuned Llama3-8b achieves 73.2% accuracy within a 20% error margin for area estimation but struggles with complex Level-3 designs. LLMs outperform the regression-based MasterRTL by 17.4% within a 5% error margin while offering 1.7x speedup by eliminating feature extraction preprocessing.",
   "checklist": {
     "artifacts": {
       "code_released": {
         "applies": true,
         "answer": true,
         "justification": "The paper provides a GitHub link: https://github.com/scale-lab/MetRex (footnote 1, Section 1)."
       },
       "data_released": {
         "applies": true,
         "answer": true,
         "justification": "The MetRex dataset of 25,868 designs is released via the same GitHub repository. The paper states the dataset is publicly available."
       },
       "environment_specified": {
         "applies": true,
         "answer": false,
         "justification": "The paper mentions hardware (A6000, A40, H100 GPUs) and 4-bit quantization, but provides no requirements.txt, Dockerfile, or detailed software environment specification with library versions."
       },
       "reproduction_instructions": {
         "applies": true,
         "answer": false,
         "justification": "No step-by-step reproduction instructions are included in the paper. The paper describes the experimental setup but does not provide commands or scripts for replication."
       }
     },
     "statistical_methodology": {
       "confidence_intervals_or_error_bars": {
         "applies": true,
         "answer": false,
         "justification": "All results in Tables 3 and 4 are reported as point estimates (e.g., '58.0%') with no confidence intervals or error bars."
       },
       "significance_tests": {
         "applies": true,
         "answer": false,
         "justification": "The paper claims improvements (e.g., 'SFT boosts... by 37.0%') based solely on comparing point estimates. No statistical significance tests are applied."
       },
       "effect_sizes_reported": {
         "applies": true,
         "answer": true,
         "justification": "The paper reports percentage improvements with baseline context (e.g., Table 4 shows both the baseline and fine-tuned acc@k values, allowing the reader to assess the magnitude of improvement)."
       },
       "sample_size_justified": {
         "applies": true,
         "answer": false,
         "justification": "The test set contains 138 designs derived from VerilogEval. No justification is provided for why this sample size is sufficient, nor is any power analysis discussed."
       },
       "variance_reported": {
         "applies": true,
         "answer": false,
         "justification": "No variance, standard deviation, or spread measures are reported across experimental runs. Results are single-run point estimates."
       }
     },
     "evaluation_design": {
       "baselines_included": {
         "applies": true,
         "answer": true,
         "justification": "The paper compares against few-shot prompted (non-finetuned) LLMs (Table 3-4) and the regression-based MasterRTL model (Section 5.4, Fig. 4)."
       },
       "baselines_contemporary": {
         "applies": true,
         "answer": true,
         "justification": "MasterRTL (2023) is the state-of-the-art regression-based approach for RTL metric estimation. Mixtral-8x7b and Llama3-8b are recent open-source models."
       },
       "ablation_study": {
         "applies": true,
         "answer": true,
         "justification": "Table 3 ablates the Chain of Thought (CoT) component, comparing performance with and without CoT prompting. The paper also varies LoRA rank (128 vs 256) in Section 5.4."
       },
       "multiple_metrics": {
         "applies": true,
         "answer": true,
         "justification": "The paper uses both MRE (Mean Relative Error, Eq. 1) and acc@k at multiple k values (1, 5, 10) and error margins (10%, 20%), applied across three metrics (area, delay, static power)."
       },
       "human_evaluation": {
         "applies": false,
         "answer": false,
         "justification": "Human evaluation is not relevant here. The ground truth comes from EDA synthesis tools, providing objective numerical targets for area, delay, and power."
       },
       "held_out_test_set": {
         "applies": true,
         "answer": true,
         "justification": "The training set (25,868 designs from RTL-Coder, VeriGen, etc.) is distinct from the test set (138 designs derived from VerilogEval benchmark), as stated in Section 5.1 and Table 2."
       },
       "per_category_breakdown": {
         "applies": true,
         "answer": true,
         "justification": "Table 2 categorizes the test set by difficulty level (L1, L2, L3), and Fig. 4 shows per-level performance comparisons between LLM and MasterRTL."
       },
       "failure_cases_discussed": {
         "applies": true,
         "answer": true,
         "justification": "Section 5.4 discusses that the model 'underperforms in level-3 primarily due to the increased reasoning complexity' and has 'higher sensitivity to variations in code design and susceptibility to generate extreme outliers.'"
       },
       "negative_results_reported": {
         "applies": true,
         "answer": true,
         "justification": "The abstract acknowledges SFT 'remains far from achieving optimal results, especially on complex problems.' Section 5.4 reports that MasterRTL outperforms the LLM under relaxed error margins (20%) and on Level-3 designs."
       }
     },
     "claims_and_evidence": {
       "abstract_claims_supported": {
         "applies": true,
         "answer": true,
         "justification": "The abstract claims of SFT improvements (37.0%, 25.3%, 25.7%) are supported by Table 4 (acc@1 deltas averaged across models). The 17.4% improvement over regression and 1.7x speedup are supported by Section 5.4 and Fig. 5."
       },
       "causal_claims_justified": {
         "applies": true,
         "answer": true,
         "justification": "The paper claims 'SFT boosts reasoning capabilities' and 'CoT prompting enhanced performance.' These causal claims are supported by controlled comparisons: CoT vs non-CoT (Table 3, same models/data) and SFT vs ICL (Table 4, same evaluation set)."
       },
       "generalization_bounded": {
         "applies": true,
         "answer": true,
         "justification": "The paper scopes its claims to Verilog HDL, post-synthesis metrics, and specific technologies (Skywater 130nm, TSMC 65nm). Section 6 explicitly acknowledges the focus on 'self-contained and relatively small-scale designs, due to the limited fine-tuning context window.'"
       },
       "alternative_explanations_discussed": {
         "applies": true,
         "answer": false,
         "justification": "The paper does not discuss alternative explanations for its results. For example, it does not consider whether the SFT improvements stem from memorization of gate-level patterns rather than genuine reasoning, or whether the CoT gains are due to format compliance rather than deeper understanding."
       },
       "proxy_outcome_distinction": {
         "applies": true,
         "answer": true,
         "justification": "The paper's claims match the granularity of its measurements. It measures MRE and acc@k on post-synthesis area/delay/power against EDA tool ground truth, and frames results in terms of 'metric estimation accuracy' without overclaiming broader capabilities."
       }
     },
     "setup_transparency": {
       "model_versions_specified": {
         "applies": true,
         "answer": false,
         "justification": "The paper refers to 'Mixtral-8x7b' and 'Llama3-8b' without specifying exact checkpoints, variant (base vs instruct), or snapshot dates. These model families have multiple versions."
       },
       "prompts_provided": {
         "applies": true,
         "answer": false,
         "justification": "Figure 2 shows the CoT template structure with a single example (full adder). However, the actual few-shot prompt text (the 10 examples), the instruction format used for SFT, and the system prompt are not fully provided."
       },
       "hyperparameters_reported": {
         "applies": true,
         "answer": true,
         "justification": "The paper reports temperature (0 for ICL, 0.4 for SFT evaluation), LoRA rank (128), 4-bit quantization, and max sequence length (1048 tokens) in Section 5.3."
       },
       "scaffolding_described": {
         "applies": false,
         "answer": false,
         "justification": "The evaluation does not use agentic scaffolding. The LLM agent mentioned in Section 4.1 is for data cleaning only, not for the main evaluation."
       },
       "data_preprocessing_documented": {
         "applies": true,
         "answer": true,
         "justification": "Section 4.1 documents the cleaning process: removing duplicates, filtering non-synthesizable elements (test benches, gate-level netlists), rectifying errors via an automated LLM agent + synthesis tool loop, and the synthesis flow using Yosys and OpenSTA."
       }
     },
     "limitations_and_scope": {
       "limitations_section_present": {
         "applies": true,
         "answer": true,
         "justification": "Section 6 ('Discussion and Future Work') contains substantive discussion of limitations including design complexity constraints, missing switching power analysis, and fixed technology assumptions."
       },
       "threats_to_validity_specific": {
         "applies": true,
         "answer": true,
         "justification": "Section 6 identifies specific limitations: the dataset focuses on 'self-contained and relatively small-scale designs, due to the limited fine-tuning context window,' switching power is excluded because it 'requires propagating the activity factor through the logic gates,' and only fixed technology node and synthesis strategy are used."
       },
       "scope_boundaries_stated": {
         "applies": true,
         "answer": true,
         "justification": "Section 6 explicitly states what was NOT tested: larger/complex designs, switching power, different synthesis strategies, and different technology nodes. The paper frames these as future work."
       }
     },
     "data_integrity": {
       "raw_data_available": {
         "applies": true,
         "answer": true,
         "justification": "The MetRex dataset is released via GitHub (https://github.com/scale-lab/MetRex), containing the Verilog designs and their post-synthesis metrics."
       },
       "data_collection_described": {
         "applies": true,
         "answer": true,
         "justification": "Section 4.1 describes data collection from six sources (RTL-Coder, VeriGen, ISCAS'89, ISCAS'85, OpenCores, NVLDA), with design counts per source in Table 1 and the synthesis methodology using Yosys and OpenSTA."
       },
       "recruitment_methods_described": {
         "applies": false,
         "answer": false,
         "justification": "No human participants are involved. Data sources are standard public datasets and benchmarks."
       },
       "data_pipeline_documented": {
         "applies": true,
         "answer": true,
         "justification": "Section 4.1 documents the full pipeline: collection from sources → duplicate removal → filtering non-synthesizable elements → automated error fixing via LLM+compiler loop → synthesis with Yosys → metric extraction via OpenSTA → CoT template generation (Section 4.2). Table 1 shows final design counts per source."
       }
     },
     "conflicts_of_interest": {
       "funding_disclosed": {
         "applies": true,
         "answer": true,
         "justification": "The acknowledgments section states: 'This work is supported by NSF grant 2350180.'"
       },
       "affiliations_disclosed": {
         "applies": true,
         "answer": true,
         "justification": "All three authors are from Brown University School of Engineering. They are not evaluating a product from their own company."
       },
       "funder_independent_of_outcome": {
         "applies": true,
         "answer": true,
         "justification": "NSF is a government funding agency with no financial stake in the outcome of this research."
       },
       "financial_interests_declared": {
         "applies": true,
         "answer": false,
         "justification": "No competing interests or financial interests statement is present in the paper."
       }
     },
     "contamination": {
       "training_cutoff_stated": {
         "applies": true,
         "answer": false,
         "justification": "The paper does not state the training data cutoff dates for Mixtral-8x7b or Llama3-8b, which is necessary to assess whether the VerilogEval test set could have been seen during pre-training."
       },
       "train_test_overlap_discussed": {
         "applies": true,
         "answer": false,
         "justification": "No discussion of whether VerilogEval test designs or similar Verilog code appeared in the pre-training data of Mixtral or Llama3."
       },
       "benchmark_contamination_addressed": {
         "applies": true,
         "answer": false,
         "justification": "VerilogEval was published in 2023. Both Mixtral and Llama3 could have been trained on data containing VerilogEval designs or their solutions, but this contamination risk is not discussed."
       }
     },
     "human_studies": {
       "pre_registered": {
         "applies": false,
         "answer": false,
         "justification": "No human participants involved. This is a benchmark evaluation study."
       },
       "irb_or_ethics_approval": {
         "applies": false,
         "answer": false,
         "justification": "No human participants involved."
       },
       "demographics_reported": {
         "applies": false,
         "answer": false,
         "justification": "No human participants involved."
       },
       "inclusion_exclusion_criteria": {
         "applies": false,
         "answer": false,
         "justification": "No human participants involved."
       },
       "randomization_described": {
         "applies": false,
         "answer": false,
         "justification": "No human participants involved."
       },
       "blinding_described": {
         "applies": false,
         "answer": false,
         "justification": "No human participants involved."
       },
       "attrition_reported": {
         "applies": false,
         "answer": false,
         "justification": "No human participants involved."
       }
     },
     "cost_and_practicality": {
       "inference_cost_reported": {
         "applies": true,
         "answer": true,
         "justification": "Figure 5 shows runtime comparison between Llama3-MetRex-8b and MasterRTL on an H100 GPU, demonstrating 1.7x speedup. Total runtimes are quantified (e.g., MasterRTL preprocessing at 505.3 seconds, model inference at 8.5 seconds)."
       },
       "compute_budget_stated": {
         "applies": true,
         "answer": false,
         "justification": "The paper mentions using a single A40 GPU for fine-tuning and a single A6000 GPU for ICL, but does not report total training time, GPU hours, or compute budget."
       }
     },
     "experimental_rigor": {
       "seed_sensitivity_reported": {
         "applies": true,
         "answer": false,
         "justification": "No multi-seed experiments are reported. Results appear to be from single training runs."
       },
       "number_of_runs_stated": {
         "applies": true,
         "answer": false,
         "justification": "The paper does not explicitly state how many training runs produced the results. The acc@k metric samples multiple predictions per design but the number of independent experimental runs is not stated."
       },
       "hyperparameter_search_budget": {
         "applies": true,
         "answer": false,
         "justification": "LoRA rank values of 128 and 256 are used, but no hyperparameter search budget, method, or total configurations tried are reported."
       },
       "best_config_selection_justified": {
         "applies": true,
         "answer": false,
         "justification": "The paper uses LoRA rank 128 for main experiments and 256 for one comparison (Section 5.4) without explaining how these values were selected or whether other configurations were tried."
       },
       "multiple_comparison_correction": {
         "applies": true,
         "answer": false,
         "justification": "Multiple comparisons are made across models, metrics (area/delay/power), error margins (10%/20%), and k values, but no correction for multiple comparisons is applied."
       },
       "self_comparison_bias_addressed": {
         "applies": true,
         "answer": false,
         "justification": "The authors compare their fine-tuned models against MasterRTL (a third-party system) but do not discuss the bias of evaluating their own system on their own benchmark."
       },
       "compute_budget_vs_performance": {
         "applies": true,
         "answer": true,
         "justification": "Figure 5 provides a runtime comparison between the LLM approach and MasterRTL, breaking down preprocessing and inference time, allowing comparison at matched runtime budgets."
       },
       "benchmark_construct_validity": {
         "applies": true,
         "answer": false,
         "justification": "The paper does not discuss whether the VerilogEval-derived test set of 138 designs is representative of real-world hardware metric estimation tasks, or whether acc@k with MRE thresholds is the right measure of reasoning capability."
       },
       "scaffold_confound_addressed": {
         "applies": false,
         "answer": false,
         "justification": "No scaffolding is involved in the evaluation. The LLMs are directly prompted or fine-tuned without agentic scaffolding."
       }
     },
     "data_leakage": {
       "temporal_leakage_addressed": {
         "applies": true,
         "answer": false,
         "justification": "Not discussed. VerilogEval was published in 2023, and both Mixtral and Llama3 could have seen VerilogEval content during pre-training."
       },
       "feature_leakage_addressed": {
         "applies": true,
         "answer": false,
         "justification": "Not discussed. The few-shot examples and CoT template could leak structural information about the expected output format, but this is not analyzed."
       },
       "non_independence_addressed": {
         "applies": true,
         "answer": false,
         "justification": "The training set includes VeriGen (GitHub-scraped Verilog) and the test set is from VerilogEval (also based on Verilog problems). Potential overlap between these sources is not discussed."
       },
       "leakage_detection_method": {
         "applies": true,
         "answer": false,
         "justification": "No leakage detection or prevention methods are applied (no deduplication between training and pre-training data, no canary strings, no membership inference)."
       }
     }
   },
   "claims": [
     {
       "claim": "Supervised Fine-Tuning boosts LLM reasoning capabilities on average by 37.0%, 25.3%, and 25.7% on area, delay, and static power respectively.",
       "evidence": "Table 4 shows acc@1 improvements for both Mixtral and Llama3 models after SFT compared to ICL baselines. E.g., Llama3-8b area acc@1 improves from 17.4% to 58.0% (+40.6%).",
       "supported": "moderate"
     },
     {
       "claim": "Chain of Thought prompting enhances ICL performance on average by 5.1%, 5.4%, and 8.9% on area, delay, and static power.",
       "evidence": "Table 3 shows acc@5 improvements when using CoT vs direct prompting for both Mixtral and Llama3 models under 10% and 20% error margins.",
       "supported": "moderate"
     },
     {
       "claim": "LLMs improve the rate of obtaining accurate estimates within a 5% error margin by 17.4% compared to MasterRTL.",
       "evidence": "Section 5.4 and Fig. 4 show per-level comparisons between Llama3-MetRex-8b and MasterRTL at 5%, 10%, and 20% error margins.",
       "supported": "moderate"
     },
     {
       "claim": "LLMs offer a 1.7x speedup by eliminating the need for preprocessing.",
       "evidence": "Figure 5 shows runtime comparison on H100 GPU. MasterRTL total time is dominated by SOG generation and feature extraction (505.3s), while LLM inference is faster overall.",
       "supported": "moderate"
     },
     {
       "claim": "Fine-tuned Llama3-MetRex-8b achieves accuracy rates of 73.2%, 61.6%, and 52.2% for area, delay, and static power within a 20% error margin.",
       "evidence": "Table 4 shows these acc@1 values for the fine-tuned Llama3-MetRex-8b model at the 20% MRE threshold.",
       "supported": "moderate"
     }
   ],
   "red_flags": [
     {
       "flag": "Training data dominated by LLM-generated code",
       "detail": "71.3% of the training dataset (18,450 of 25,868 designs) comes from RTL-Coder, which contains GPT-generated Verilog. This could bias the model toward patterns in LLM-generated code rather than human-written designs, potentially inflating metrics on the test set which also includes programmatically-derived designs."
     },
     {
       "flag": "Small test set without uncertainty quantification",
       "detail": "The test set contains only 138 designs. Per-level subsets are even smaller (L1: 23, L2: 43, L3: 72). No confidence intervals, error bars, or statistical tests are reported, making it impossible to assess whether observed differences are statistically significant."
     },
     {
       "flag": "No contamination analysis",
       "detail": "Both Mixtral and Llama3 could have seen VerilogEval designs (published 2023) during pre-training. Additionally, the training data sources (VeriGen from GitHub) could overlap with VerilogEval. No deduplication or contamination analysis is performed."
     },
     {
       "flag": "Selective comparison with MasterRTL",
       "detail": "The comparison with MasterRTL in Fig. 4 shows the LLM is better at 5% margin but MasterRTL is better at 20% margin and on complex designs. The abstract and conclusion emphasize the 5% and 17.4% advantage while downplaying the regression model's strengths on harder problems."
     }
   ],
   "cited_papers": [
     {
       "title": "Benchmarking large language models for automated verilog rtl code generation",
       "authors": ["Shailja Thakur", "Baleegh Ahmad", "Zhenxing Fan", "Hammond Pearce", "Benjamin Tan", "Ramesh Karri", "Brendan Dolan-Gavitt", "Siddharth Garg"],
       "year": 2023,
       "relevance": "Benchmarks LLMs on Verilog code generation, directly related to evaluating LLM capabilities on hardware design tasks."
     },
     {
       "title": "Invited paper: Verilogeval: Evaluating large language models for verilog code generation",
       "authors": ["Mingjie Liu", "Nathaniel Pinckney", "Brucek Khailany", "Haoxing Ren"],
       "year": 2023,
       "relevance": "Provides the VerilogEval benchmark used as the test set in this paper; key benchmark for LLM-based Verilog generation evaluation."
     },
     {
       "title": "RTLLM: An open-source benchmark for design RTL generation with large language model",
       "authors": ["Yao Lu", "Shang Liu", "Qijun Zhang", "Zhiyao Xie"],
       "year": 2024,
       "relevance": "Another benchmark for evaluating LLMs on RTL code generation, relevant to understanding LLM capabilities in hardware design."
     },
     {
       "title": "RTLFixer: Automatically fixing RTL syntax errors with large language models",
       "authors": ["YunDa Tsai", "Mingjie Liu", "Haoxing Ren"],
       "year": 2023,
       "arxiv_id": "2311.16543",
       "relevance": "Uses LLMs for automated RTL bug fixing; the automated cleaning flow in MetRex is inspired by this approach."
     },
     {
       "title": "Evaluating large language models trained on code",
       "authors": ["Mark Chen", "Jerry Tworek", "Heewoo Jun"],
       "year": 2021,
       "arxiv_id": "2107.03374",
       "relevance": "Introduces the pass@k metric and Codex evaluation; foundational work for evaluating LLM code generation capabilities."
     },
     {
       "title": "CruxEval: A benchmark for code reasoning, understanding and execution",
       "authors": ["Alex Gu", "Baptiste Rozière", "Hugh Leather", "Armando Solar-Lezama", "Gabriel Synnaeve", "Sida I Wang"],
       "year": 2024,
       "arxiv_id": "2401.03065",
       "relevance": "Benchmarks LLM code reasoning and execution capabilities, closely related to the code metric reasoning task addressed here."
     },
     {
       "title": "ChatEDA: A large language model powered autonomous agent for EDA",
       "authors": ["Haoyuan Wu", "Zhuolun He", "Xinyun Zhang", "Xufeng Yao", "Su Zheng", "Haisheng Zheng", "Bei Yu"],
       "year": 2024,
       "relevance": "Demonstrates LLM-powered autonomous agent for electronic design automation, relevant to agentic AI in hardware design."
     },
     {
       "title": "MasterRTL: A pre-synthesis PPA estimation framework for any RTL design",
       "authors": ["Wenji Fang", "Yao Lu", "Shang Liu", "Qijun Zhang", "Ceyu Xu", "Lisa Wu Wills", "Hongce Zhang", "Zhiyao Xie"],
       "year": 2023,
       "relevance": "The primary regression-based baseline used for comparison; state-of-the-art ML approach for RTL metric estimation."
     },
     {
       "title": "Chain-of-thought prompting elicits reasoning in large language models",
       "authors": ["Jason Wei", "Xuezhi Wang", "Dale Schuurmans"],
       "year": 2022,
       "relevance": "Foundational work on chain-of-thought prompting that MetRex builds upon for its CoT template design."
     },
     {
       "title": "RTLCoder: Outperforming GPT-3.5 in design RTL generation with our open-source dataset and lightweight solution",
       "authors": ["Shang Liu", "Wenji Fang", "Yao Lu", "Qijun Zhang", "Hongce Zhang", "Zhiyao Xie"],
       "year": 2024,
       "relevance": "Source of the largest portion of MetRex training data (18,450 LLM-generated Verilog designs); evaluates fine-tuned LLMs for RTL generation."
     },
     {
       "title": "LoRA: Low-rank adaptation of large language models",
       "authors": ["Edward J Hu", "Phillip Wallis", "Zeyuan Allen-Zhu"],
       "year": 2021,
       "relevance": "The parameter-efficient fine-tuning technique used in all MetRex SFT experiments."
     },
     {
       "title": "Meta large language model compiler: Foundation models of compiler optimization",
       "authors": ["Chris Cummins", "Volker Seeker", "Dejan Grubisic", "Baptiste Roziere", "Jonas Gehring", "Gabriel Synnaeve", "Hugh Leather"],
       "year": 2024,
       "arxiv_id": "2407.02524",
       "relevance": "Applies LLMs to compiler optimization, demonstrating LLM capabilities in code reasoning and optimization tasks."
     }
   ],
   "engagement_factors": {
     "practical_relevance": {
       "score": 1,
       "justification": "Hardware designers could potentially use this for early metric estimation, but accuracy is limited and the approach requires fine-tuning."
     },
     "surprise_contrarian": {
       "score": 1,
       "justification": "Novel application of LLMs to Verilog metric estimation, but the finding that LLMs can estimate numerical properties with CoT is not deeply surprising."
     },
     "fear_safety": {
       "score": 0,
       "justification": "No safety or security implications; purely a hardware design productivity tool."
     },
     "drama_conflict": {
       "score": 0,
       "justification": "No controversy; straightforward benchmark introduction paper."
     },
     "demo_ability": {
       "score": 2,
       "justification": "GitHub repository with dataset and code is available; a researcher with GPU access could replicate the fine-tuning experiments."
     },
     "brand_recognition": {
       "score": 0,
       "justification": "Brown University is respected but not a high-profile AI lab; no major brand products involved."
     }
   }
 }